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Wireless power transfer (WPT) technology, with its unique advantage of contactless energy delivery, has been widely adopted in fields such as electric vehicle charging and power supply for deep-sea exploration equipment[1,2]. A typical WPT system employs numerous power electronic devices, which may fail under harsh operational conditions, leading to system malfunction. Thus, research on fault diagnosis for WPT systems holds significant theoretical and practical importance. Current academic efforts in this area can be broadly classified into three categories: fault-tolerant control, machine learning, and signal processing.
Fault-tolerant control methods enhance system reliability through topology and control optimization. For instance, a dual-coupled LCC-S topology was introduced to achieve fault tolerance by utilizing the mutual inductance characteristics of coils[3], whereas another approach localized short-circuit faults via series sampling resistors at a relatively high cost[4]. Multi-transmitter/receiver architectures can enhance fault tolerance through redundant design[5,6]. Additionally, systems with incipient faults have been parameterized and stabilized using observer-based controllers[7−9]. However, these strategies primarily serve as emergency responses after a fault occurs, mitigating its impact without locating or eliminating the root cause.
Machine learning methods often abstract key units such as inverters, resonators, and rectifiers into independent subsystems. By collecting electrical parameters before and after a fault to build training datasets, artificial intelligence algorithms like backpropagation neural networks and support vector machines are applied to extract fault features, enabling defect identification in S-S and LCC-S type WPT systems[10]. Although this approach avoids complex physical modeling, it faces notable limitations: fault feature extraction is tightly coupled to specific system topologies, algorithm performance is highly sensitive to sample size, and heavy reliance on large labeled datasets restricts cross-topology transferability and real-time diagnostic efficiency.
To address the dependence of machine learning on massive training data, one study collected gate signals and switch currents under various operating conditions, employed rough set theory for feature extraction and redundancy removal, converted the results into logical expressions, and implemented fault diagnosis using digital logic modules[11], albeit with considerable diagnostic complexity. Another work designed a novel rectifier topology that maintains efficient operation under diode open-circuit conditions and diagnosed faults based on the appearance of a DC bias under failure, which is absent during normal operation[12]. Nevertheless, this solution has not been verified for switching device faults.
Power switch faults are generally categorized into short-circuit (SC) and open-circuit (OC) types. SC faults can normally be cleared by fast-acting fuses, whereas OC faults do not cause immediate system breakdown but increase electrical stress on healthy components, potentially leading to abnormal operation or damage over time. Based on the above analysis, this paper proposes a signal-processing method utilizing DC bus voltage and switch driving signal for diagnosis and localization of power switch OC fault in the WPT system. The remainder of the paper is organized as follows: firstly, analyzing the system transmission characteristics under the single-tube OC fault condition; secondly, designing the signal processing method based on the current path, and realizing the diagnosis and localization of the OC fault by identifying the disappearance of the specific voltage characteristics under the fault condition; and lastly, verifying the validity of the method through experiments.
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Figure 1 shows a typical S-S type WPT system used for fault diagnosis analysis in this paper. In this system, Uo is a DC voltage source, and the inductance L1 and capacitance C5 form a DC-side LC filter circuit. The stray inductance Ls is composed of the equivalent series inductance of C5 and the line inductance. S1 to S4 are IGBT modules, with their respective anti-parallel diodes being D1 to D4 and parasitic capacitances being C1 to C4. These components collectively form a single-phase full-bridge inverter circuit. RT, LT, and CT are the equivalent series resistance, resonant inductance, and resonant capacitance of the transmitter-side circuit, respectively. RR, LR, and CR are the equivalent series resistance, resonant inductance, and resonant capacitance of the receiver-side circuit, respectively. M is the mutual inductance. Diodes D5 to D8, together with filter capacitor C6, form a single-phase uncontrolled rectifier circuit. RL is the load, and RE = π2/8RL is the equivalent resistance of the rectifier circuit[13]. The equivalent input impedance Zin of the system can be expressed as:
Figure 1.
A typical S-S type WPT system circuit topology diagram used for analysis in this paper.
$ {Z}_{\text{in}}={R}_{\text{T}}+j(\omega {L}_{\text{T}}-1/\omega {C}_{\text{T}})+\dfrac{{(\omega M)}^{2}}{{R}_{\text{R}}+{R}_{\text{E}}+j(\omega {L}_{\text{R}}-1/\omega {C}_{\text{R}})} $ (1) where, ω is the operating angular frequency of the system.
Analysis of the main current paths in system ZVS operating mode
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In the WPT system, to reduce switching losses, a phase-shift control strategy is typically used to operate the system in zero-voltage switching (ZVS) mode. Figure 2a shows the steady-state operating waveform of the system's inverter circuit output. Define Udc as the input voltage of the inverter circuit. Under ideal conditions, ignoring the dead time td and various losses, the output voltage of the inverter circuit can be characterized by the phase shift angle δ:
Figure 2.
Main current paths in the inverter circuit. (a) Inverter steady-state output waveform diagram. (b) Current paths in different operating modes within half a cycle. (b1) Mode 1, corresponding to t0−t1. (b2) Mode 2, corresponding to t1−t2. (b3) Mode 3, corresponding to t2−t3. (b4) Mode 4, corresponding to t3−t4. (b5) Mode 5, corresponding to t4−t5.
$ {U}_{\text{in}}=\dfrac{2\sqrt{2}{U}_{\text{dc}}\cos (\delta /2)}{\text{π}} $ (2) When the system is operating normally, its current flow path corresponds to ten operating modes. To simplify the analysis process, this paper only focuses on the operating mode of the positive half-cycle of the current, as shown in Fig. 2b.
Mode 1, corresponding to the t0−t1 time interval: Apply drive signals to S1 and S4, and the current flows along the path S1 → transmitter side circuit → S4.
Mode 2, corresponding to the t1−t2 time interval: Apply a drive signal to S4, and S1 is turned off in ZVS mode. At this point, the current flows through two paths: one path flows through C1 → transmitter side circuit → S4 to charge C1, and the other path flows through C2 → transmitter side circuit → S4 to discharge C2, preparing for the ZVS conduction of S2. To ensure the ZVS margin, assuming that C1 = C2 = C3 = C4 = Coes, we have[14]:
$ {t}_{12}=\dfrac{2{C}_{\text{oes}}{U}_{\text{dc}}}{{I}_{\text{Tm}}}\leq \dfrac{{t}_{\text{d}}}{2} $ (3) where, t12 is the duration of this mode.
Mode 3, corresponding to the t2−t3 time interval: Apply drive signals to S2 and S4. Since the IGBT module cannot conduct in reverse, the current flows through the path D2 → transmitter side circuit → S4.
Mode 4, corresponding to the t3−t4 time interval: Apply a drive signal to S2. Since the IGBT module cannot conduct in reverse, the current flows through two paths at this time: one path flows through D2 → transmitter side circuit → C4 to charge C4, and the other path flows through D2 → transmitter side circuit → C3 to discharge C3, preparing for S3 ZVS conduction. To achieve system ZVS, it is necessary to ensure that Zin exhibits resistive-inductive characteristics. Additionally, in engineering applications, a margin of 10~15° is typically reserved to meet the following relationship:
$ \arctan ({Z}_{\text{in}})=(10\sim 15){^{\circ}}+\dfrac{\delta +\omega {t}_{\text{d}}}{2} $ (4) Mode 5, corresponding to the t4−t5 time interval: Apply drive signals to S2 and S3. Since the IGBT module cannot conduct in reverse, the current flows through the path D2 → transmitter side circuit → D3.
System transmission characteristics analysis
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(1) Normal working conditions
The transmission efficiency of the WPT system can be defined by the system output power Pout and the total system power loss Ploss:
$ \eta =\dfrac{{P}_{\text{out}}}{{P}_{\text{out}}+{P}_{\text{loss}}}=\dfrac{{(2{{I}_{\text{Rm}}}/\text{π})}^{2}{\mathrm{R}}_{\text{L}}}{{(2{{I}_{\text{Rm}}}/\text{π})}^{2}{R}_{\text{L}}+{P}_{\text{loss}}} $ (5) where, IRm is the maximum value of the system receiver-side loop current iR. The following section presents calculations for Ploss, which consist of four parts: LC filter circuit loss, inverter circuit loss, resonance compensation circuit loss, and rectifier circuit loss.
LC filter circuit loss: This loss is the thermal loss generated by the equivalent series resistance rL1 of the L1 branch and the equivalent series resistance rC5 of the C5 branch, denoted as PL1 and PC5, respectively. Assuming that Udc remains constant, the above two losses can be expressed as:
$ {P}_{\text{L1}}={I}_{\text{o}}{}^{2}{r}_{\text{L1}}\approx {\left(\dfrac{{I}_{\text{Tm}}}{\sqrt{2}}\right)}^{2}{r}_{\text{L1}} $ (6) $ {P}_{\text{C5}}={\left(\dfrac{{I}_{\text{Tm}}}{\sqrt{2}}-{{I}_{\text{o}}}\right)}^{2}{r}_{\text{C5}} $ (7) where, Io is the current output from the voltage source, and ITm is the maximum value of the transmitter-side loop current iT of the system.
Inverter circuit loss: This loss consists of three parts: the conduction loss Prs, turn-on loss Pton, and turn-off loss Ptoff of the IGBT module. Among these, Prs is the thermal loss generated by the conduction resistance rIGBT of the switching transistor, Pton is the thermal loss generated during the charging and discharging process of the capacitance Cce between the collector and emitter of the IGBT, and Ptoff is the power loss generated by the overlap of voltage and current during the turn-off process of the IGBT. The three components satisfy the following relationships[15]:
$ {P}_{\text{rs}}={\left(\dfrac{{I}_{\text{Tm}}}{\sqrt{2}}\right)}^{2}{r}_{\text{IGBT}} $ (8) $ {P}_{\text{ton}}=10f{C}_{\text{ce}}\sqrt{U_{\text{dc}}^{3}} $ (9) $ {P}_{\text{toff}}=f{U}_{\text{dc}}\dfrac{{I}_{\text{Tm}}}{\sqrt{2}}\left(\dfrac{{t}_{\text{r}}}{3}+\dfrac{{t}_{\text{f}}}{2}\right) $ (10) where, f is the operating frequency of the system, tr is the voltage rise time of the switching transistor, and tf is the current fall time.
Resonance compensation circuit loss: This loss, Pcomp, consists of thermal losses generated by the equivalent series resistance of the transmit and receive side loops:
$ {P}_{\text{comp}}={\left(\dfrac{{I}_{\text{Tm}}}{\sqrt{2}}\right)}^{2}{R}_{\text{T}}+{\left(\dfrac{{I}_{\text{Rm}}}{\sqrt{2}}\right)}^{2}{R}_{\text{R}} $ (11) Rectifier circuit loss: This loss consists of two parts: diode power loss PD and C6 branch loss PC6. PD is caused by the power loss resulting from the forward voltage drop UD of the diode and the thermal loss generated by the forward resistance rD. PC6 is the thermal loss generated by the equivalent series resistance rC6 of the branch where C6 is located. The two meet the following relationships:
$ {P}_{\text{D}}={U}_{\text{D}}\dfrac{I_\text{Rm}}{\text{π}}+{\left(\dfrac{I_\text{Rm}}{2}\right)}^{2}{r}_{\text{D}} $ (12) $ {P}_{\text{C6}}={\left(\dfrac{2}{\text{π}}{{I}_{\text{Rm}}}\right)}^{2}\left(\dfrac{{\text{π}}^{2}}{8}-1\right){r}_{\text{C6}} $ (13) Substituting Eqs. (6)−(13) into Eq. (5) yields the following expression for the system transmission efficiency:
$ \eta =\dfrac{{P}_{\text{out}}}{{P}_{\text{L1}}+{P}_{\text{C5}}+2{P}_{\text{rs}}+4{P}_{\text{ton}}+4{P}_{\text{toff}}+{P}_{\text{comp}}+4{P}_{\text{D}}+{P}_{\text{C6}}+{P}_{\text{out}}} $ (14) (2) Inverter circuit single tube OC fault condition
Assuming an OC fault occurs in S2, the primary current flow path in the system changes from the normal state of D1D4 → S1S4 → D2S4 → D2D3 → S2S3 → D1S3 to D1D4 → S1S4 → D2S4 → D2D3 → D1S3, as shown in Fig. 3. During the negative half-cycle, the conductive path formed by D2D3 causes the inverter circuit to produce a reverse output voltage with a duration of t45, as shown in Fig. 3b. This mode persists until the output current crosses zero in the reverse direction. t45 can be approximately by the switching tube leakage current Ioff:
Figure 3.
PWM waveforms of switching devices under different operating conditions. (a) Normal working conditions. (b) S2 OC fault condition.
$ {t}_{45}=\dfrac{{I}_{\text{off}}\mathrm{Im}({Z}_{\text{in}})}{{U}_{\text{in}}-{\mathrm{I}}_{\text{off}}\mathrm{Re}({Z}_{\text{in}})}\approx \dfrac{{I}_{\text{off}}{L}_{\text{in}}}{{U}_{\text{in}}} $ (15) Since the typical value of Ioff is 10 to 100 μA, t45 can be neglected relative to the entire switching cycle under high voltage conditions. At this point, the output voltage of the inverter circuit after a single tube OC fault becomes:
$ {U}_{\text{in}}'=\dfrac{\sqrt{2}{U}_{\text{dc}}\cos (\delta /2)}{\text{π}} $ (16) From Eqs. (2) and (16), it can be deduced that after a fault occurs, the RMS value of the inverter circuit output voltage drops to half of the normal operating condition, causing ITm and IRm to drop to half of their original values. Considering that only three switching transistors are involved in the operation of the inverter circuit during the fault state, Eq. (14) becomes:
$ {\eta }^{\prime}=\dfrac{{P}_{\text{out}}}{ {P}_{\text{L1}}+{P}_{\text{C5}}+({{I}_{\text{Tm}}}/\sqrt{2})^{2}{r}_{\text{C5}}+3{P}_{\text{rs}}/2+12{P}_{\text{ton}}+6{P}_{\text{toff}}+{P}_{\text{comp}}+4{P}_{\text{D}}+ 4{U}_{\text{D}}{I}_{\text{Rm}}/\text{π}+{P}_{\text{C6}}+{P}_{\text{out}}} $ (17) In Eq. (17), Pout dominates. Comparing with Eq. (14), it can be seen that the system efficiency decreases slightly after the fault, while the output power drops significantly to about one-quarter of the normal operating condition. In actual experiments, the specific numerical value of the efficiency reduction is difficult to measure precisely, but the significant decrease in output power can intuitively demonstrate the impact of an OC fault on the system's transmission performance, thereby highlighting the necessity of diagnosis. Simultaneously, such abrupt characteristics in transmission performance can also serve as supplementary verification for diagnostic results. In summary, the impact of a single-tube OC fault on transmission characteristics manifests as follows:
$ \begin{cases} {P}_{\text{out}}'=\dfrac{1}{4}{P}_{\text{out}}\\ {\eta }^{\prime} \lt \eta \end{cases} $ (18) -
The equivalent circuit of the WPT system used to establish the diagnostic model is shown in Fig. 4. The two arms of the inverter circuit are defined as the leading-leg and lagging-leg, respectively, and the switching function can be expressed as:
Figure 4.
Equivalent circuit topology of the WPT system used to establish the diagnostic model.
$ {S }_{x}=\begin{cases} 1,({S}_{\text{upper}},{S}_{\text{lower}})=(1,0)\\ 0,({S}_{\text{upper}},{S}_{\text{lower}})=(0,1) \end{cases} x=\text{leading-leg},\text{lagging-leg} $ (19) where, Supper (Slower) for the upper (lower) switching tube of the bridge arm.
The input current idc of the inverter circuit is composed of the current flowing through the leading-leg or lagging-leg:
$ {i}_{\text{dc}}=\sum\limits_{x}{S }_{x}{i}_{x} $ (20) When Sx remains constant, the system is considered to be in a steady state, and the voltage UC5 across C5 is equal to Uo. When Sx changes, the system is considered to be in a transient state, and Uo = UL1 + UC5 − ULS, so the voltages across L1 and LS satisfy the following relationship:
$ {U}_{\text{L1}}={U}_{\text{LS}} $ (21) Since the equivalent input impedance of the system remains unchanged, ix remains constant when the system is in the steady state, while idc undergoes instantaneous changes when the system becomes transient[16]:
$ \dfrac{d{i}_{\text{dc}}}{dt}=\Delta {S }_{x}\dfrac{d{i}_{\text{s}}}{dt} $ (22) where, is is the current during the turn-on or turn-off process of the switching transistor.
According to Kirchhoff's current law, the change in idc is composed of the change in current iL1 in L1 and the change in current iC5 in C5, while the changes in iL1 and iC5 generate induced voltages at the two ends of L1 and LS, respectively:
$ \begin{cases} \dfrac{d{i}_{\text{dc}}}{dt}=\dfrac{d{i}_{\text{L1}}}{dt}+\dfrac{d{i}_{\text{C5}}}{dt}\\ {U}_{\text{L1}}={L}_{1}\dfrac{d{i}_{\text{L1}}}{dt}\\ {U}_{\text{LS}}={L}_{\text{S}}\dfrac{d{i}_{\text{C5}}}{dt} \end{cases} $ (23) Since LS is much smaller than L1, it can be ignored. According to Eqs. (21) and (23), we obtain:
$ {U}_{\text{LS}}={L}_{\text{S}}\dfrac{{L}_{1}}{{L}_{1}+{L}_{\text{S}}}\cdot \dfrac{d{i}_{\text{dc}}}{dt}\approx {L}_{\text{S}}\dfrac{d{i}_{\text{dc}}}{dt} $ (24) The DC bus voltage Udc consists of two mutually opposite voltages, UC5 and ULS:
$ {U}_{\text{dc}}={U}_{\text{C5}}-{L}_{\text{S}}\dfrac{d{i}_{\text{dc}}}{dt} $ (25) As can be seen from Eq. (25), when the system is in a steady state, Udc remains relatively constant. When entering a transient state, Udc will accompany the corresponding pulse. Since the system operates in an underdamped mode, the pulse exhibits an oscillatory decay waveform characteristic, which can serve as a basis for fault diagnosis.
DC bus voltage characteristics based on switch drive signals
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In system operating mode, the time required for parasitic capacitance charging and discharging is negligible compared to other modes. When analyzing the switching transistor turn-on and turn-off processes, both the leading-leg and the lagging-leg can exhibit the six operating conditions distinguished by the positive and negative values of ix on the left side of Fig. 5. This paper only discusses the three typical cases where ix > 0.
Figure 5.
Main current paths of the WPT system diagnostic model under different operating conditions. ix > 0: (a) Sx = 1; (b) Sx = 1 to 0; (c) Sx = 0; (d) Supper OC. ix < 0: (e) Sx = 0; (f) Sx = 0 to 1; (g) Sx = 1; (h) Slower OC.
Sx = 1 condition: For a single bridge arm, ix is conducted through the upper tube Supper on that bridge arm.
Sx = 0 condition: Since the IGBT cannot conduct in reverse, ix conducts through diode Dlower.
Sx = 1 to 0 condition: When Sx jumps from 1 to 0, Supper gradually shuts down, accompanied by the gradual conduction of the anti-parallel diode Dlower on the lower tube of the bridge arm. At this point, the following relationship is satisfied:
$ \begin{cases} {i}_{x}={i}_{xa}+{i}_{xb}\\ \dfrac{d{i}_{\text{dc}}}{dt}=\dfrac{d{i}_{xa}}{dt} \lt 0 \end{cases} $ (26) where, ixa and ixb represent the currents flowing through Supper and Dlower during the turn-off process, respectively.
Substituting Eq. (26) into Eq. (25) yields the following: When Sx undergoes a transition, Udc generates a corresponding positive pulse, followed by an oscillatory decay characteristic. When an OC fault occurs in the switch, if Supper is open-circuited, under the condition of ix > 0, regardless of how Sx changes, ix can only flow through Dlower, as shown in Fig. 5d. At this point, didc/dt = 0, and the aforementioned pulse characteristics of Udc disappear. However, under the condition of ix < 0, current can still flow through Dupper or Slower, unaffected by the fault, so Udc retains its corresponding pulse characteristics. Similarly, if Slower is open-circuited, under the condition of ix < 0, ix can only be conducted through Dupper, and the pulse characteristics of Udc will also disappear. Therefore, by combining the disappearance of the DC bus voltage characteristics with the switch drive signals, precise diagnosis and localization of switch transistor OC faults can be achieved.
Fault diagnosis and localization strategy for the WPT system
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Based on the above analysis, the WPT system power switch OC fault diagnosis and localization strategy flowchart proposed in this paper is shown in Fig. 6, as follows:
Figure 6.
Flowchart of WPT system fault diagnosis and localization strategy.
Step 1: Signal acquisition. First, define the switch function change quantity, which satisfies the following relationship:
$ \Delta {S }_{x}={S }_{x}({t}_{k})-{S }_{x}({t}_{k-1})\;\text{where},\;\Delta {S }_{x}\in \{-1,0,1\} $ (27) where, tk-1 denotes the last sampling point before time tk.
Since Udc does not have a characteristic waveform when ΔSx = 0, but exhibits the aforementioned pulse oscillation characteristics when ΔSx = ±1, it is only necessary to collect the DC bus voltage signal Udc (tf) corresponding to the moment when ΔSx = ±1.
Step 2: Fault diagnosis. If the collected Udc (tf) exhibits the aforementioned voltage characteristics, it is determined that the system's inverter circuit is functioning normally, and under normal operating conditions, Udc typically exhibits four such characteristics within one cycle T. If the voltage characteristics of Udc (tf) disappear, it is determined that the system may have an OC fault in the power switch, and the fault verification process is initiated. If the characteristics of Udc (tf + T) and Udc (tf + 2T) disappear in the subsequent two cycles, the power switch OC fault is confirmed, and the process proceeds to the next step of fault localization. Otherwise, the system is still deemed to be operating normally. In actual experiments, the diagnostic threshold can be set reasonably to simplify the judgment logic. When the pulse amplitude of Udc (tf) is below this threshold, it is considered that the characteristic is missing.
Step 3: Fault location. Combining the timing information of Udc (tf), it is possible to first determine whether the fault occurred in the leading-leg or the lagging-leg. Further combining this with the positive or negative nature of ΔSx, it is possible to locate the specific fault power switch. If ΔSx > 0, it is determined to be Slower fault; if ΔSx < 0, it is determined to be Supper fault.
Auxiliary verification step: Achieved by monitoring sudden characteristics in system transmission performance. If the system output power drops significantly to approximately one-quarter of the normal value while efficiency decreases slightly, this indicates an OC fault has occurred.
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To validate the proposed method in this paper, an experimental platform as shown in Fig. 7 was constructed. Parameter measurements were performed using an Agilent E4980A LCR meter. The specific system parameter configuration is listed in Table 1, with parameter design satisfying the system input impedance constraints specified in Eq. (4). The inverter circuit employs the Infineon IKW75N65RH5 IGBT module, while the rectifier circuit utilizes the ThinkiSemi MUR40120PT fast recovery diode. In the experiment, the distance between the transmitting and receiving coils varied between 50 and 200 mm. The coupling coefficient k, calculated based on the measured mutual inductance, ranged from 0.384 to 0.098. According to the IGBT module datasheet, its equivalent output capacitance Coes is approximately 460 pF. The td was set to 551 ns to satisfy the constraint requirement in Eq. (3).
Figure 7.
Experimental platform for method validation.
Table 1. Experimental platform parameters.
Parameters Value Parameters Value Uo (V) 80 f (kHz) 70 δ (°) 19 td (ns) 551 L1 (mH) 0.3 rL1 (Ω) 0.002 C5 (mF) 0.5 rC5 (Ω) 0.013 LS (nH) 218 rIGBT (Ω) 0.06 tr (ns) 9 tf (ns) 15 Cce (pF) 445 M (μH) 4.2~16.5 RT (Ω) 0.06 RR (Ω) 0.07 LT (μH) 42.7 LR (μH) 43.2 CT (nF) 128.8 CR (nF) 120.1 UD (V) 1.7 rD (Ω) 0.005 C6 (μF) 50.2 rC6 (Ω) 0.005 RL (Ω) 5.5~20.1 k 0.098~0.384 The method of simulating an OC fault in the switching transistor via drive signal control from the host computer has been thoroughly validated[17]. This approach is also employed in the experiments described herein. Figure 8a−c, and d−f, respectively display the key electrical waveforms during normal system operation and S2 OC fault conditions, with a coil spacing of 100 mm. The phase relationship between uin and iT in Fig. 8b and e confirm the system operates in ZVS mode. Following the fault, the negative half-cycle of uin nearly vanishes. Combining Fig. 8b, c, e, and f reveals that both ITm and IRm decrease by approximately 50% post-fault. From the measured data in Fig. 8a−c, the normal operating conditions yield Uo = 80 V, Io = 18 A, ITm = 26.3 A, IRm = 16 A, and URL = 114.9 V. Calculations based on these values indicate an output power of 1,269.424 W under normal conditions, with an actual operating efficiency of 88.2%. Substituting the normal operating electrical parameters into Eq. (14) yields a theoretical system efficiency of 90.6%, which closely matches the actual efficiency. Substituting the normal operating electrical parameters into Eq. (17) yields a theoretical efficiency of 88.3% after the system failure. As shown by the measured data in Fig. 8d and f, the actual efficiency after the failure is 84%, which is consistent with the theoretical analysis results, validating the conclusion of a slight decrease in efficiency post-failure. Simultaneous calculations show the pre- and post-fault output powers to be 1,269.424 and 309.124 W, respectively. The post-fault output power drops to approximately one-quarter of the pre-fault value, consistent with the theoretical analysis results presented earlier, thereby providing supplementary verification of the occurrence of an OC fault.
Figure 8.
Relevant electrical parameters for power and efficiency calculations. (a)–(c) Normal operating case. (d)–(f) S2 OC case. (a) DC voltage source output voltage Uo and output current Io. (b) Load voltage URL, inverter circuit output voltage uin, and transmitter-side loop current iT. (c) receiver-side loop current iR. (d) DC voltage source output voltage Uo' and output current Io'. (e) Load voltage URL', inverter circuit output voltage uin', and transmitter-side loop current iT'. (f) receiver-side loop current iR'.
Figure 9 shows the DC bus voltage and drive signal waveforms for burst OC faults in each power switch under different coupling coefficients when the load resistance is fixed at 10.4 Ω. Taking the S2 OC fault in Fig. 9a as an example: during normal operation, when the switching function Sx remains constant, Udc stays relatively stable with minor noise; When Sx undergoes a sudden change, Udc exhibits pronounced pulsed oscillation characteristics. After the fault occurs, the number of characteristic pulses generated within one cycle due to ΔSx changes decreases from 4 to 3. By analyzing the timing relationship of the drive signal, it can be determined that the characteristic corresponding to Sleading-leg arm has disappeared. Furthermore, since ΔSx > 0, the fault is further localized to the lower switch of this arm, i.e., S2 is open-circuited. Based on the same diagnostic strategy, accurate diagnosis and localization are achieved for other OC faults of power switches shown in Fig. 9b−d, as well as for fault waveforms under different loads with a fixed coupling coefficient of 0.235, shown in Fig. 10, validating the effectiveness of the proposed method.
Figure 9.
Experimental results for OC fault in each switching transistor under different coupling coefficients. (a) k = 0.384, S2 OC case. (b) k = 0.235, S1 OC case. (c) k = 0.158, S4 OC case. (d) k = 0.098, S3 OC case.
Figure 10.
Experimental results for OC fault in each switching transistor under different load resistances. (a) RL = 5.5Ω, S4 OC case. (b) RL = 10.4Ω, S3 OC case. (c) RL = 15.7Ω, S1 OC case. (d) RL = 20.1Ω, S2 OC case.
During the experiment, the Udc signal was acquired using a high-voltage differential probe and simultaneously recorded by a SIGLENT SDS H12 Pro digital oscilloscope (sampling rate: 125 MSa/s). Additionally, to meet the requirements for long-term, high-speed data acquisition and online processing, a Yokogawa DL850E oscilloscope recorder (maximum sampling rate 100 MSa/s) was simultaneously employed for waveform recording. Based on this data, the diagnostic algorithm shown in Fig. 6 was executed, with results uploaded to the upper computer via a communication interface. In practical applications, since the required fault characteristics appear only during the instantaneous switching action, an intermittent sampling strategy can be adopted to effectively reduce the demand for continuous sampling rates in the system.
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Given the current lack of thorough research on fault diagnosis for WPT systems, this paper comprehensively compares several DC bus voltage-based diagnostic methods in the power electronics field over recent years. The comparison is conducted across four dimensions—feature parameters, diagnostic time, cost, and judgment logic—to highlight the superiority of the proposed strategy. As shown in Table 2, the primary advantage of the proposed method lies in its straightforward diagnostic logic. To mitigate noise interference and ensure accuracy, it achieves precise fault localization within two to three switching cycles. Furthermore, as illustrated in Fig. 8, pulse oscillations are also observed on the inverter circuit output side when applying this method. This finding indicates that sufficient electrical margin must be reserved during switch device selection and driver circuit design. In subsequent work, the proposed method may struggle to precisely capture subtle electrical signal changes caused by device aging. Therefore, we will explore integrating machine learning methods to adaptively optimize diagnostic thresholds and achieve diagnosis of aging states resulting from device performance degradation.
Table 2. Performance comparison of similar methods.
Ref. Feature parameters Diagnosis time Software and hardware costs Logical judgment [18] DC bus voltage difference residual Three switching cycles Medium Comlex [19] DC capacitor voltage One current cycle Medium Moderate [20] DC bus voltage, output current Half to two current cycles Small Moderate [21] DC bus voltage, three-phase current One switching cycle Large Moderate Proposed DC bus voltage Three switching cycles Small Simple -
This paper first analyzes the transmission characteristics of a WPT system when a single power switch experiences an OC fault. Subsequently, based on the current path when the system operates in ZVS mode, a fault diagnosis method for power switches is proposed using DC bus voltage and switch drive signals. This method achieves fault diagnosis and localization by identifying the disappearance of DC bus voltage characteristics. Experimental results confirm that the system's transmission characteristics post-fault align with theoretical analysis. When an OC fault occurs in the WPT system's power switch, the proposed method enables rapid and accurate fault localization within two to three switching cycles.
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The authors confirm their contributions to the paper as follows: study conception and design: Chen C, Wang Z, Yu Y; data collection: Deng Q, Wang F; analysis and interpretation of results: Chen C, Wang F, Yu Y; draft manuscript preparation: Wang F, Wang Z. All authors reviewed the results and approved the final version of the manuscript.
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The datasets generated during and/or analyzed during the current study are available from the corresponding author upon reasonable request.
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This work was supported in part by the National Natural Science Foundation of China under (Grant No. 52377128).
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The authors declare that they have no conflict of interest.
- Copyright: © 2026 by the author(s). Published by Maximum Academic Press, Fayetteville, GA. This article is an open access article distributed under Creative Commons Attribution License (CC BY 4.0), visit https://creativecommons.org/licenses/by/4.0/.
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Cite this article
Chen C, Wang F, Wang Z, Yu Y, Deng Q. 2026. Research on diagnosis of open-circuit fault in power switch of WPT system based on DC bus voltage and switch driving signal. Wireless Power Transfer 13: e020 doi: 10.48130/wpt-0026-0009 
Research on diagnosis of open-circuit fault in power switch of WPT system based on DC bus voltage and switch driving signal
- Received: 02 September 2025
- Revised: 22 December 2025
- Accepted: 28 February 2026
- Published online: 02 July 2026
Abstract: Wireless power transfer (WPT) technology finds extensive applications in areas such as powering deep-sea exploration equipment. However, due to harsh operating environments, core components such as power switches are prone to failure, leading to system malfunctions. To address system abnormalities caused by open-circuit faults in WPT system power switches, this paper proposes a fault diagnosis method based on DC bus voltage and switch drive signals. First, the primary current paths during normal operation in zero-voltage switching mode are analyzed. The impact of a single power switch failure on system transmission characteristics is investigated, revealing that the fault reduces output power to approximately one-quarter while efficiency shows a slight decline. Second, a DC bus voltage model for the WPT system is established based on the current paths. By leveraging the disappearance of post-fault voltage characteristics in conjunction with switch drive signals, precise fault diagnosis and localization can be achieved. Finally, an experimental platform was constructed under different coupling conditions and load scenarios. Through simulating an open-circuit fault of the power switch, the impact of the fault on system transmission performance and the effectiveness of the proposed diagnostic method are verified.
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Key words:
- Wireless power transfer /
- Power switch /
- Open-circuit fault /
- Fault diagnosis /
- Fault location